CW308T-S6LX9 - Revision history

Coflynn: Replaced content with "== Page Moved == See [https://rtfm.newae.com/Targets/UFO%20Targets/CW308T-S6LX9/ NewAE RTFM Page] which is now built from the [https://github.com/newaetech/chipwhisperer-..."

2020-07-29T19:22:03Z

Replaced content with "== Page Moved == See [https://rtfm.newae.com/Targets/UFO%20Targets/CW308T-S6LX9/ NewAE RTFM Page] which is now built from the [https://github.com/newaetech/chipwhisperer-..."

Fheubach at 18:17, 1 May 2018

2018-05-01T18:17:35Z

Cwiesner: /* Programming */

2018-02-15T18:45:13Z

‎Programming

Coflynn: /* Programming */

2018-01-26T16:31:12Z

‎Programming

Coflynn: /* Usage */

2018-01-26T16:26:52Z

‎Usage

Coflynn at 16:51, 5 October 2017

2017-10-05T16:51:42Z

Coflynn: /* Programming */

2017-10-05T16:37:49Z

‎Programming

Coflynn: /* Example Project */

2017-10-05T16:30:04Z

‎Example Project

Coflynn: /* Example Project */

2017-10-05T16:28:18Z

‎Example Project

Coflynn: /* Example Project */

2017-10-05T16:09:29Z

‎Example Project

@@ Line 1: / Line 1: @@
-{{Infobox cw308target
+== Page Moved ==
-|name                   = CW308T-S6LX9
-|image                  = File:S6LX9-Top.jpg
-|caption                =
-|Target Device          = Spartan 6 LX9
-|Target Architecture    = FPGA
-|Hardware Crypto        = No
-|Purchase Hardware      = [http://store.newae.com/spartan-6-lx9-fpga-target-for-cw308/ Webstore]
-|Design Files           = [https://github.com/newaetech/chipwhisperer/tree/master/hardware/victims/cw308_ufo_target/spartan6lx9 GITHub link]
-[https://oshpark.com/shared_projects/ECbBlx58 OSH Park PCBs]
+See [https://rtfm.newae.com/Targets/UFO%20Targets/CW308T-S6LX9/ NewAE RTFM Page] which is now built from the [https://github.com/newaetech/chipwhisperer-target-cw308t GIT Repo].
-|Supported Applications = [[SimpleSerial | Simple Serial Enc]]
-|Programmer             = Xilinx JTAG
-|Status                 = Released
-}}
-The S6LX9 target is a low-cost FPGA target. It uses the Xilinx Spartan 6 in TQFP package (XC6SLX9-2TQG144C), and can fit an entire AES core. The example project includes the Simple-Serial interface which allows it to function like any of our other example targets.
+The previous content on this wiki has been moved to the above link. See wiki history if you would like to view exact older versions of this page.
-−
-== Usage ==
-−
-The board includes a single red LED (D1) which is connected to the FPGA "DONE" pin. This pin will be HIGH (and the LED on) when the FPGA is NOT programmed. That is to say immediately on power-on, the LED will be on. Once the FPGA is successfully programmed this LED will go out.
-−
-The FPGA pins are connected to the various headers on the board. The JTAG header connects to the FPGA JTAG pins. The "Hx" pins, USART, and SPI connect to arbitrary FPGA pins.
-−
-'''NB: You MUST enable the 1.2V regulator when using this board. The 1.2V power LED should be ON. This is easily done by toggling the position of the 1.2V LDO switch (to either come from the 3.3V from CW-Lite, or external power depending on your setup).
-'''
-−
-== Example Project ==
-−
-The GIT repo includes an example Xilinx ISE project, located at [https://github.com/newaetech/chipwhisperer/tree/develop/hardware/victims/cw308_ufo_target/spartan6lx9/ss_aes_ise hardware/victims/cw308_ufo_target/spartan6lx9/ss_aes_ise]. To use this project:
-−
-# Build the bitstream (or see the pre-built one in the repo at [https://github.com/newaetech/chipwhisperer/raw/develop/hardware/victims/cw308_ufo_target/spartan6lx9/ss_aes_ise/cw308t_s6lx9_example.bit cw308t_s6lx9_example.bit])
-# Use settings as in the 'Default XMEGA' or 'STM32Fx' targets (i.e., clock jumpers, etc).
-# Ensure you have turned on the 1.2V & 3.3V power supplies to the UFO target.
-# Program the bitstream into the FPGA using a programming tool such as Xilinx Impact + USB Programmer cable.
-# Run the 'XMEGA Simple-Serial' script in ChipWhisperer-Capture. This will setup clocks, serial data format, etc as expected.
-# Adjust the trigger offset settings - they should be changed to around ~750, and you can reduce the number of data points to ~128.
-−
-The waveform should look something like this:
-−
-[[File:s6lx9_waveform.png|400px]]
-−
-{{Warningbox|There appears to be occasional jitter on the default AES core, so you might need to use re-synchronization on the power traces. See the [https://github.com/newaetech/chipwhisperer/issues/72 GITHub issue track].}}
-−
-== Known Issues ==
-−
-Note the -02 Revision of the PCB has swapped the markings of the CLKIN/CLKOUT. The correct pinout is:
-−
-* CLKIN connects to P84
-* CLKOUT connects to P85
-−
-The CLKIN pin is a _N clock pin. If you need the _P clock pin, you can use a jumper on the CW308 board to route the clock input into the CLKOUT pin.
-−
-== Programming ==
-−
-The ChipWhisperer will eventually support programming this target. Until then, you will need an external programmer. This is connected via JTAG to the pin headers:
-−
-[[File:s6lx9_jtag.jpg|400px]]
-−
-Options for programmers include:
-−
-* Xilinx Platform Cable USB or USB-II (Digikey/Mouser).
-* Clone JTAG programmers off AliExpress/E-Bay for low cost (search 'Xilinx JTAG').
-* Digilent Inc HS1/HS2/HS3 Cables (NB: you may need separate jumper wires).
-−
-To use IMPACT:
-−
-* Generate a new project.
-* Assign the .bit file to the FPGA (say 'no' to attached SPI flash chips).
-* Program.
-−
-[[File:s6lx9_program.png|400px]]
-−
-== Schematic ==
-−
-See GIT Repo for PDF of schematic.
-−
-[[File:CW308T_S6LX9_Schematic_Page_1.png|1000px]]
-−
-[[File:CW308T_S6LX9_Schematic_Page_2.png|1000px]]
-−
-[[File:CW308T_S6LX9_Schematic_Page_3.png|1000px]]
-−
-== Board Layout ==
-−
-See GIT Repo for gerber files.
-−
-== Hardware ==
-−
-{{Template:Hardware}}
-[[Category: CW308 Targets]]

@@ Line 85: / Line 85: @@
 See GIT Repo for gerber files.
 {{Template:Hardware}}
 [[Category: CW308 Targets]]

@@ Line 56: / Line 56: @@
 The ChipWhisperer will eventually support programming this target. Until then, you will need an external programmer. This is connected via JTAG to the pin headers:
-[[File:xilinx_jtag_small.jpg|400px]]
+[[File:s6lx9_jtag.jpg|400px]]
-−
-{{Warningbox|Connect TDI as well to the TDI pin - this is a MISTAKE in the above photo!}}
 Options for programmers include:

← Older revision		Revision as of 16:31, 26 January 2018
Line 57:		Line 57:

	[[File:xilinx_jtag_small.jpg\|400px]]		[[File:xilinx_jtag_small.jpg\|400px]]
		+
		+	{{Warningbox\|Connect TDI as well to the TDI pin - this is a MISTAKE in the above photo!}}

	Options for programmers include:		Options for programmers include:

← Older revision		Revision as of 16:26, 26 January 2018
Line 22:		Line 22:

	The FPGA pins are connected to the various headers on the board. The JTAG header connects to the FPGA JTAG pins. The "Hx" pins, USART, and SPI connect to arbitrary FPGA pins.		The FPGA pins are connected to the various headers on the board. The JTAG header connects to the FPGA JTAG pins. The "Hx" pins, USART, and SPI connect to arbitrary FPGA pins.
		+
		+	'''NB: You MUST enable the 1.2V regulator when using this board. The 1.2V power LED should be ON. This is easily done by toggling the position of the 1.2V LDO switch (to either come from the 3.3V from CW-Lite, or external power depending on your setup).
		+	'''

	== Example Project ==		== Example Project ==