Tutorial CW305-1 Building a Project - Revision history

Fheubach at 18:52, 1 May 2018

2018-05-01T18:52:15Z

Fheubach at 14:34, 1 May 2018

2018-05-01T14:34:54Z

Coflynn at 16:47, 25 March 2017

2017-03-25T16:47:17Z

Coflynn: /* Capture Setup */

2017-01-20T19:39:49Z

‎Capture Setup

Coflynn: /* Capture Setup */

2017-01-19T20:50:00Z

‎Capture Setup

Coflynn: /* Building the Project */

2017-01-19T20:37:54Z

‎Building the Project

Coflynn: /* Target Firmware */

2017-01-19T20:32:59Z

‎Target Firmware

Coflynn: /* Opening the Project */

2017-01-19T20:31:23Z

‎Opening the Project

Coflynn: /* Opening the Project */

2017-01-19T20:30:26Z

‎Opening the Project

Coflynn: /* CW305 Hardware */

2017-01-19T20:29:49Z

‎CW305 Hardware

@@ Line 95: / Line 95: @@
 </ol>
 For further analysis using this project, check out the next tutorial: [[Tutorial CW305-2 Breaking AES on FPGA]].
 {{Template:Tutorials}}
 [[Category:Tutorials]]

@@ Line 1: / Line 1: @@
 The CW305 target is an FPGA target board for use with the ChipWhisperer capture hardware. This board lets you test side channel analysis techniques on an Artix-7 FPGA. With this setup, a different toolchain is required: we won't be building C firmware with a makefile. This tutorial walks through the various steps required to run an AES-128 example on the CW305 target.
-= CW305 Hardware =
+== CW305 Hardware ==
 If you're used to working with the ChipWhisperer Lite XMEGA or the UFO targets, the CW305 board will feel a bit different. Rather than sending data through a UART directly from the capture hardware, we'll now use two separate connections to the target board.
@@ Line 14: / Line 14: @@
 [[File:CW305_CWLite_SCA.jpg|800px]]
-= Target Firmware =
+== Target Firmware ==
 In the ChipWhisperer examples, the Artix-7 FPGA is programmed using Verilog. This section describes how to open and build one of these projects. It also describes the layout of the AES-128 example, which is a good starting point for making new FPGA projects.
 Note if you just want to follow along with the rest of the tutorials, you can use the pre-built bitstream (<code>.bit</code> file). In which case simply skip ahead to any of the following tutorials.
-== Opening the Project ==
+=== Opening the Project ===
 The first thing we'll need is [https://www.xilinx.com/support/download.html Xilinx Vivado HLx], which is their FGPA design software. The fully featured versions of this software require a $3000+ license. However, the WEBPACK version is free, with the limitation that it can only be used with 4 families of devices (including the Artix-7). This is a huge download, so get it started while you read (possibly also you'll have time for lunch and a few drinks).
@@ Line 34: / Line 34: @@
 This is enough for us to start poking around in the code.
-== FPGA Code Layout ==
+=== FPGA Code Layout ===
 If you're planning on making your own projects for side channel analysis, it's helpful to understand how the sample project is set up. Here's a high-level description of the different pieces:
@@ Line 43: / Line 43: @@
 * <code>aes_core.v</code>: The AES core module is an implementation of AES from Google. This is taken from the [https://github.com/ProjectVault/orp/tree/master/hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_aes/rtl/verilog ProjectVault repository].
-== Building the Project ==
+=== Building the Project ===
 This project is already fully built for us. However, if you want to make your own project, you'll need to know how to build it. There are three steps that Vivado takes to turn our Verilog into a fully functional piece of code:
@@ Line 57: / Line 57: @@
 }}
-= Capture Setup =
+== Capture Setup ==
 With our FPGA bitstream in hand, we're now ready to capture a power trace. We can set this up using the ChipWhisperer Capture software.

@@ Line 52: / Line 52: @@
 This process can take a while - on an average laptop, the sample project takes around 7 minutes to build.
-{{Infobox|'''Gotcha''': This project can be implemented to fit into an Artix-7A35T or an Artix-7A100T chip. Make sure that you have the correct one selected (right click -> "Make Active") before you build the project:
+{{Warningbox|'''Gotcha''': This project can be implemented to fit into an Artix-7A35T or an Artix-7A100T chip. Make sure that you have the correct one selected (right click -> "Make Active") before you build the project:
 [[File:CW305MakeActive.png]]

@@ Line 62: / Line 62: @@
 <ol style="list-style-type: decimal;">
-<li>We'll need to set up the DIP switches on the CW305. These are the four switches next to the 20-pin connector. We need to set two of them for this project:
+<li><p>We'll need to set up the DIP switches on the CW305. These are the four switches next to the 20-pin connector. We need to set two of them for this project:
 * '''J16: 0''' - use the on-board PLL to clock the FPGA
 * '''K16: 1''' - route the FPGA's clock to the ChipWhisperer's HS-In channel
-The other two switches have no effect on the clock routing, so they can be in either position.</li>
+The other two switches have no effect on the clock routing, so they can be in either position.</p></li>
-<li>Next, we need to set up the software. To make this process simple, there is an existing sample script that connects to the CW305 using the ChipWhisperer Lite. This script is located in <code>Project -> Example Scripts -> CW305 Artix Target w/ ChipWhisperer-Lite</code>
+<li><p>Next, we need to set up the software. To make this process simple, there is an existing sample script that connects to the CW305 using the ChipWhisperer Lite. This script is located in <code>Project -> Example Scripts -> CW305 Artix Target w/ ChipWhisperer-Lite</code></p>
-[[File:CW305Script.png|800px]]
+<p>[[File:CW305Script.png|800px]]</p>
-This script will connect to the CW305 and ChipWhisperer Lite, setting them up for a capture.
+<p>This script will connect to the CW305 and ChipWhisperer Lite, setting them up for a capture.</p>
 </li>
-<li>
+<li><p>
-The FPGA bitstream needs to be programmed onto the Artix board. There is a button called "Program FPGA" that takes a bitstream (specified the line above that button) and programs it into the FPGA.
+The FPGA bitstream needs to be programmed onto the Artix board. There is a button called "Program FPGA" that takes a bitstream (specified the line above that button) and programs it into the FPGA.</p>
-[[File:CW305Bitstream.PNG]]
+<p>[[File:CW305Bitstream.PNG]]</p>
 </li>
 <li>
-Select the bitstream file that we generated earlier (<code>chipwhisperer/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_35t/cw305_top.bit</code>) and program it onto the FPGA. If using the '''100T''' size FPGA, you will find the file in a directory labeled '''impl_100t''' instead.
+<p>Select the bitstream file that we generated earlier (<code>chipwhisperer/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_35t/cw305_top.bit</code>) and program it onto the FPGA. If using the '''100T''' size FPGA, you will find the file in a directory labeled '''impl_100t''' instead.</p>
-NOTE: Even if you haven't completed the build portion, you can simply use the pre-built bitstream!
+<p>NOTE: Even if you haven't completed the build portion, you can simply use the pre-built bitstream!</p>
 </li>
 <li>
-Now, the Capture 1 button should give us a short and sweet power trace:
+<p>Now, the Capture 1 button should give us a short and sweet power trace:</p>
-[[File:CW305SampleCapture.PNG|800px]]
+<p>[[File:CW305SampleCapture.PNG|800px]]</p>
-Success! We've built a project and recorded a power trace using the Artix target.
+<p>Success! We've built a project and recorded a power trace using the Artix target.</p>
 </li>
 </ol>

@@ Line 60: / Line 60: @@
 With our FPGA bitstream in hand, we're now ready to capture a power trace. We can set this up using the ChipWhisperer Capture software.
-The first thing we need to do is set up the DIP switches on the CW305. These are the four switches next to the 20-pin connector. We need to set two of them for this project:
+<ol style="list-style-type: decimal;">
 * '''J16: 0''' - use the on-board PLL to clock the FPGA
 * '''K16: 1''' - route the FPGA's clock to the ChipWhisperer's HS-In channel
-Next, we need to set up the software. To make this process simple, there is an existing sample script that connects to the CW305 using the ChipWhisperer Lite. This script is located in <code>Project -> Example Scripts -> CW305 Artix Target w/ ChipWhisperer-Lite</code>:
+The other two switches have no effect on the clock routing, so they can be in either position.</li>
 [[File:CW305Script.png|800px]]
-This script will connect to the CW305 and ChipWhisperer Lite, setting them up for a capture. Once the script is finished, there's one more step that we need to take - the FPGA bitstream needs to be programmed onto the Artix:
+This script will connect to the CW305 and ChipWhisperer Lite, setting them up for a capture.
 [[File:CW305Bitstream.PNG]]
-Select the bitstream file that we generated earlier (<code>chipwhisperer/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_35t/cw305_top.bit</code>) and program it onto the FPGA. Now, the Capture 1 button should give us a short and sweet power trace:
+NOTE: Even if you haven't completed the build portion, you can simply use the pre-built bitstream!
 [[File:CW305SampleCapture.PNG|800px]]
 Success! We've built a project and recorded a power trace using the Artix target.
+</li>
 For further analysis using this project, check out the next tutorial: [[Tutorial CW305-2 Breaking AES on FPGA]].
 {{Template:Tutorials}}
 [[Category:Tutorials]]

@@ Line 18: / Line 18: @@
 == Opening the Project ==
-The first thing we'll need is [https://www.xilinx.com/support/download.html Xilinx Vivado HLx], which is their FGPA design software. The fully featured versions of this software require a $3000+ license. However, the WEBPACK version is free, with the limitation that it can only be used with 4 families of devices (including the Artix-7). This is a huge download, so get it started while you read (possibly also have lunch).
+The first thing we'll need is [https://www.xilinx.com/support/download.html Xilinx Vivado HLx], which is their FGPA design software. The fully featured versions of this software require a $3000+ license. However, the WEBPACK version is free, with the limitation that it can only be used with 4 families of devices (including the Artix-7). This is a huge download, so get it started while you read (possibly also you'll have time for lunch and a few drinks).
 For this tutorial, a pre-existing AES-128 encryption example is waiting for us deep inside the ChipWhisperer repository. You can find this at <code>chipwhisperer\hardware\victims\cw305_artixtarget\fpga\vivado_examples\aes128_verilog</code>. There are a couple of files and directories here:

@@ Line 8: / Line 8: @@
 # We'll control the Artix-7 directly from the laptop via USB. This is done through the USB-B port on the left side of the board. (On the target, the Atmel SAM3U chip converts these USB packets into signals that the FPGA can understand.)
 # We'll get control information for our power measurements through the 20-pin connector at the bottom of the board. This needs to be connected to your capture hardware (a ChipWhisperer Lite or Pro).
-# Our power measurements will be done through an SMA cable. Depending on your capture setup, there are three SMA connectors that allow access to the power line in three ways (before the shunt resistor, after the shunt, and after a low noise amplifier). For the ChipWhisperer hardware, we'll connect the third one to our capture board.
+# Our power measurements will be done through an SMA cable. Depending on your capture setup, there are three SMA connectors that allow access to the power line in three ways (before the shunt resistor, after the shunt, and after a low noise amplifier). For the ChipWhisperer hardware, we'll connect the third one to our capture board. This provides a nice amplified signal we can pick off.
 Using a ChipWhisperer Lite, the full hardware setup looks like: