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− | {{Infobox cw308target
| + | == Page Moved == |
− | |name = CW308T-CEC1702
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− | |image = File:CEC1702_Wiki.PNG
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− | |caption =
| + | |
− | |Target Device = MCHP CEC1702
| + | |
− | |Target Architecture = ARM Cortex M4F
| + | |
− | |Hardware Crypto = AES, SHA, RSA
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− | |Purchase Hardware =
| + | |
− | |Supported Applications = []
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− | |Programmer = Generic SPI Flash Programmer
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− | |Status = In Development
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− | }}The CEC1702 is an embedded controller with strong cryptographic support, customized for Internet of Things (IOT) platforms. The chip implements a highly-configurable, mixed signal, advanced I/O controller architecture. The device incorporates a 32-bit ARM Cortex M4F Microcontroller core with closely-coupled SRAM for code and data. A secure boot-loader is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The CW308T-CEC1702 incorporates the main chip with a 16MB SPI flash chip and a bi-directional SPI Buffer. The target board has standard power monitoring, UART serial, and clock In/Out compatibility with the CW308. JTAG pins and many GPIO pins are also exposed for prototyping and testing use.
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− | == I/O Connections ==
| + | See [https://rtfm.newae.com/Targets/UFO%20Targets/CW308T-CEC1702/ NewAE RTFM Page] which is now built from the [https://github.com/newaetech/chipwhisperer-target-cw308t GIT Repo]. |
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− | {| class="wikitable"
| + | The previous content on this wiki has been moved to the above link. See wiki history if you would like to view exact older versions of this page. |
− | !CW308 Pin
| + | |
− | !CEC1702 Pin
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− | !Function
| + | |
− | |-
| + | |
− | |GPIO1
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− | |P104 (TXD0)
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− | |Serial OUTPUT from CEC1702
| + | |
− | |-
| + | |
− | |GPIO2
| + | |
− | |P105 (RXD0)
| + | |
− | |Serial INPUT to CEC1702
| + | |
− | |-
| + | |
− | |GPIO3
| + | |
− | |P030
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |GPIO4
| + | |
− | |P017
| + | |
− | |Trigger pin
| + | |
− | |-
| + | |
− | |CLKIN
| + | |
− | |XTAL2
| + | |
− | |Optional CLKIN
| + | |
− | |-
| + | |
− | |CLKFB
| + | |
− | |P002 (PWM5)
| + | |
− | |Can output 12MHz PWM on this pin. Useful for synchronizing to internal oscillator
| + | |
− | |-
| + | |
− | |J_TRST
| + | |
− | |JTAG_RST
| + | |
− | |JTAG Reset
| + | |
− | |-
| + | |
− | |J_TDI
| + | |
− | |JTAG_TDI
| + | |
− | |JTAG TDI
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− | |-
| + | |
− | |J_TDO
| + | |
− | |JTAG_TDO
| + | |
− | |JTAG TDO
| + | |
− | |-
| + | |
− | |J_TMS
| + | |
− | |JTAG_TMS
| + | |
− | |JTAG TMS
| + | |
− | |-
| + | |
− | |J_TCK
| + | |
− | |JTAG_CLK
| + | |
− | |JTAG Clock
| + | |
− | |-
| + | |
− | |LED1
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− | |P156
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− | |GPIO, Breathing LED0
| + | |
− | |-
| + | |
− | |LED2
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− | |P157
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− | |GPIO, Breathing LED1
| + | |
− | |-
| + | |
− | |LED3
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− | |PA7
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− | |GPIO, LED
| + | |
− | |-
| + | |
− | |PDIC
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− | |
| + | |
− | |SPI buffer output enable, drive high to enable SPI programming and sniffing
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− | |-
| + | |
− | |PDID/CS
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− | |QSPI0_CS
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− | |SPI chip select for SPI flash chip
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− | |-
| + | |
− | |H1
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− | |P040
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− | |GPIO
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− | |-
| + | |
− | |H2
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− | |P031
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H3
| + | |
− | |P026
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H4
| + | |
− | |P053
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H5
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− | |P054
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H6
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− | |P027
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H7
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− | |P107
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− | |GPIO
| + | |
− | |-
| + | |
− | |H8
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− | |P120
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− | |GPIO
| + | |
− | |-
| + | |
− | |H9
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− | |P112
| + | |
− | |GPIO
| + | |
− | |-
| + | |
− | |H10
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− | |P113
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− | |GPIO
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− | |}
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− | | + | |
− | == Hardware Cryptography ==
| + | |
− | '''Multi-purpose AES Cryptographic Engine'''
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− | - Hardware support for ECB, CTR, CBC, and OFB AES modes
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− | - Support for 128-bit, 192-bit and 256-bit key length
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− | - DMA interface to SRAM, shared with Hash engine
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− | | + | |
− | '''Cryptographic Hash Engine'''
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− | - Support for SHA-1, SHA-256, SHA-512
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− | - DMA interface to SRAM, shared with AES engine
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− | | + | |
− | '''Public Key Cryptographic Engine'''
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− | - Hardware support for RSA and Elliptic Curve public key algorithms
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− | - RSA keys length from 1024 to 4096 bits
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− | - ECC Prime Field and Binary Field keys up to 640 bits
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− | - Microcoded support for standard public key algorithms
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− | | + | |
− | '''Cryptographic Features'''
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− | - True Random Number Generator
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− | - 1 Kbit FIFO
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− | - Monotonic Counter
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