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→Capture Setup
With our FPGA bitstream in hand, we're now ready to capture a power trace. We can set this up using the ChipWhisperer Capture software.
* '''J16: 0''' - use the on-board PLL to clock the FPGA
* '''K16: 1''' - route the FPGA's clock to the ChipWhisperer's HS-In channel
The other two switches have no effect on the clock routing, so they can be in either position.</li> <li>Next, we need to set up the software. To make this process simple, there is an existing sample script that connects to the CW305 using the ChipWhisperer Lite. This script is located in <code>Project -> Example Scripts -> CW305 Artix Target w/ ChipWhisperer-Lite</code>:
[[File:CW305Script.png|800px]]
This script will connect to the CW305 and ChipWhisperer Lite, setting them up for a capture. Once the script is finished, there's one more step that we need to take - the </li> <li>The FPGA bitstream needs to be programmed onto the Artix:board. There is a button called "Program FPGA" that takes a bitstream (specified the line above that button) and programs it into the FPGA.
[[File:CW305Bitstream.PNG]]
</li>
<li>
Select the bitstream file that we generated earlier (<code>chipwhisperer/hardware/victims/cw305_artixtarget/fpga/vivado_examples/aes128_verilog/aes128_verilog.runs/impl_35t/cw305_top.bit</code>) and program it onto the FPGA. If using the '''100T''' size FPGA, you will find the file in a directory labeled '''impl_100t''' instead.
[[File:CW305SampleCapture.PNG|800px]]
Success! We've built a project and recorded a power trace using the Artix target.
</li></ol>
For further analysis using this project, check out the next tutorial: [[Tutorial CW305-2 Breaking AES on FPGA]].
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