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→Opening the Project
== Opening the Project ==
The first thing we'll need is [https://www.xilinx.com/support/download.html Xilinx Vivado HLx], which is their FGPA design software. The fully featured versions of this software require a $3000+ license. However, the WEBPACK version is free, with the limitation that it can only be used with 4 families of devices (including the Artix-7).
To get us started, a pre-existing AES-128 encryption example is waiting for us deep inside the ChipWhisperer repository. You can find this at <code>chipwhisperer\hardware\victims\cw305_artixtarget\fpga\vivado_examples\aes128_verilog</code>. There are a couple of files and directories here:
* <code>aes128_verilog.xpr</code> is the project file. You can open this project using Vivado.* <code>aes128_verilog.srcs\</code> contains Verilog source files for the project. Note that most of the code for this project is stored elsewhere - take a look at <code>cw305_artixtarget\fpga\common\</code> and <code>cw305_artixtarget\fpga\cryptosrc\</code> too.* <code>aes128_verilog.runs\</code> contains the compiled output that is synthesized in Vivado. The most important part of this output is the bitstream (a .bit file), which is what we'll upload onto the target board. When you open the project file, you should be greeted with a screen like: [[File:CW305Vivado.PNG|800px]] This is enough for us to start poking around in the code.
== FPGA Code Layout ==