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This advanced tutorial will demonstrate the use of analog Sum of Absolute Difference (SAD) triggering system. The SAD trigger can be used to trigger an event (e.g. capture or glitch) based on a pattern in the analog waveform. This pattern typically comes from the Device Under Test (DUT) performing an operation of interest such as cryptographic or authentication code.
The SAD trigger is built into the [[CW1002_ChipWhisperer_Capture_Rev2]] only at this time, and is not present in the [[CW1173_ChipWhisperer-Lite]].
== The SAD Criteria ==
The Sum of Absolute Differences (SAD) measures the similarity between two blocks of data. This is done simply by first subtracting the two arrays in an element-wise fashion, then converting that into an absolute value, and finally summing up the absolute difference between each element. You can see other examples of the [http://en.wikipedia.org/wiki/Sum_of_absolute_differences SAD Algorithm on Wikipedia].
In this system, a trigger is generated whenever the output of the SAD algorithm falls below some threshold. The FPGA calculates the SAD critera for every incoming sample, where the SAD is calculated over 128 samples. The following diagram shows the system design:
[[File:sad_diagram.png|image]]
Both the reference waveform and the input must have the same scaling. For example if you are using the SAD trigger module, you cannot adjust the analog gain on the input without recording a new reference waveform.
== Using the SAD Trigger ==
Currently the SAD Trigger is demonstrated in this video:
[[File:/youtube-sad.png|link=http://www.youtube.com/watch?v=qnKxOpGRo-Q&hd=1]]
The SAD trigger is built into the [[CW1002_ChipWhisperer_Capture_Rev2]] only at this time, and is not present in the [[CW1173_ChipWhisperer-Lite]].
== The SAD Criteria ==
The Sum of Absolute Differences (SAD) measures the similarity between two blocks of data. This is done simply by first subtracting the two arrays in an element-wise fashion, then converting that into an absolute value, and finally summing up the absolute difference between each element. You can see other examples of the [http://en.wikipedia.org/wiki/Sum_of_absolute_differences SAD Algorithm on Wikipedia].
In this system, a trigger is generated whenever the output of the SAD algorithm falls below some threshold. The FPGA calculates the SAD critera for every incoming sample, where the SAD is calculated over 128 samples. The following diagram shows the system design:
[[File:sad_diagram.png|image]]
Both the reference waveform and the input must have the same scaling. For example if you are using the SAD trigger module, you cannot adjust the analog gain on the input without recording a new reference waveform.
== Using the SAD Trigger ==
Currently the SAD Trigger is demonstrated in this video:
[[File:/youtube-sad.png|link=http://www.youtube.com/watch?v=qnKxOpGRo-Q&hd=1]]