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Created page with " The CW1173 contains two 8-pin connectors, which use our standard 8-pin Smart-Card header pinout. One header connects to the SAM3U device (which has ISO-7816 drivers), one hea..."
The CW1173 contains two 8-pin connectors, which use our standard 8-pin Smart-Card header pinout. One header connects to the SAM3U device (which has ISO-7816 drivers), one header connects to the FPGA. Note there is currently no firmware support for these devices, but the hardware is designed for any of the following:
* Emulating a smart card (use interposer board), or fuzzing a smart card reader
* Communicating to a smart card
* Sniffing traffic between a legitimate reader and smart card
* Side-channel analysis of smart card device
Header J7 (Connects to SAM3U):
{| class="wikitable"
! Number
! Name
! Dir
! Description
|-
| 1
| VCCIO
| O
| 3.3V Supply (from linear regulator, always on)
|-
| 2
| GND
| O
| System GND
|-
| 3
| RST
| I/O
| Reset (SAM3U: PA3)
|-
| 4
| PRESENT
| I
| Used to detect presence of smart card (SAM3U: PA2)
|-
| 5
| CLK
| I/O
| Clock (SAM3U: PA25, 'CLK2'. FPGA: P131)
|-
| 6
| I/O
| I/O
| I/O Line (SAM3U: PA22), 10k pull-up
|-
| 7
| AUX1
| I/O
| Spare line (SAM3U: PA4)
|-
| 8
| AUX2
| I/O
| Spare line (SAM3U: PA5)
|}
Header J6 (Connects to FPGA):
{| class="wikitable"
! Number
! Name
! Dir
! Description
|-
| 1
| VCCIO
| O
| 3.3V Supply (from FPGA supply)
|-
| 2
| GND
| O
| System GND
|-
| 3
| RST
| I/O
| Reset (FPGA: P102)
|-
| 4
| PRESENT/VPP
| I
| Not Connected (mount R60 to connect to P101)
|-
| 5
| CLK
| I/O
| Clock (FPGA: P100)
|-
| 6
| I/O
| I/O
| I/O Line (FPGA: P99), 10k pull-up
|-
| 7
| AUX1
| I/O
| Spare line (FPGA: P98)
|-
| 8
| AUX2
| I/O
| Spare line (FPGA: P97)
|}
