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→FPGA Configuration
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== Python Example ==
Note: The following examples reference the
=== Connecting and Programming ===
cw = CW305()
cw.con(bsfile=r"C:\chipwhisperer\hardware\victims\cw305_artixtarget\fpga\vivado_examples\aes128_verilog\aes128_verilog.runs\impl_35t\cw305_top.bit", force=False)
</syntaxhighlight>The optional "bsfile" argument causes it to download a bitstream. If the "force" flag is set to "False", the system will only download the bitstream to an UNPROGRAMMED FPGA. You can use the force flag to ensure your FPGA is always reconfigured (or if was corrupted, has been recovered).
If doing development, you probably want to set the force flag to "True". This will ensure you always get a newly programmed FPGA with the latest bitstream.
