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Tutorial CW305-2 Breaking AES on FPGA

6 bytes added, 20:13, 16 January 2017
Theoretical Background
In our case, let's suppose that every round of AES is completed in a single clock cycle. Recall the execution of AES:
[[File:AES_Encryption.png|600px]]
Here, every blue block is executed in one clock cycle. This means that an excellent candidate for a CPA attack is the difference between the input and output of the final round. It is likely that this state is stored in a port that is updated every round, so we expect that the Hamming distance between the round input and output is the most important factor on the power consumption. Also, the last round is the easiest to attack because it has no MixColumns operation. We'll use this Hamming distance as the target in our CPA attack.
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